1. Field of the Invention
The present invention relates to a field-effect transistor such as a thin-film transistor and to a manufacturing method therefor. Further, the present invention relates to a manufacturing method for a display device using the field-effect transistors and to a display device manufactured using the manufacturing method for the display device. More specifically, the present invention relates to a field-effect transistor such as a thin-film transistor having a gate electrode, a source electrode, and a drain electrode of the thin-film transistor simultaneously formed by patterning a same starting film by use of photolithography and to a manufacturing method therefor.
2. Description of the Related Art
Hereinbelow, an example of a conventional manufacturing procedure for a thin-film transistor will be described. An amorphous silicon film is formed on the upper side of a glass substrate, the amorphous silicon film is crystallized, and a crystalline silicon film is thereby formed. Then, the crystalline silicon film is patterned into an island-like crystalline silicon film, and a gate insulation film is formed on the island-like crystalline silicon film. Subsequently, a conductive film formed on the gate insulation film is patterned, and a gate electrode is thereby formed. Then, using the gate electrode as a mask, an impurity is introduced to the island-like crystalline silicon film by using an ion doping method, and a source region and a drain region are thereby formed. Next, a first interlayer insulation film is formed on both the gate electrode and the island-like crystalline silicon film. Then, an opening (contact hole) is formed by performing patterning on the first interlayer insulation film so as to reach the source region and the drain region. Thereafter, a conductive film to be connected to the source region and the drain region is formed, and the conductive film is then patterned. Thereby, a source electrode and a drain electrode are formed. The thin-film transistor is manufactured according to the above-described procedure. The aforementioned procedure is well known (Refer to, for example, a patent document 1 below). When applying the thin-film transistor manufactured according to the well-known art to a pixel portion of a display device, a second interlayer insulation film is formed on both the source electrode and the drain electrode, and an opening is formed by performing patterning so as to reach one of the source electrode and the source electrode. In addition, a transparent conductive film is formed and patterned, and a pixel electrode is then formed.
(Patent Document 1)
Japanese Patent Application Laid-open No. Hei 8-330602 (FIGS. 1A to 1F; First Embodiment)
As described above, according to the conventional procedure, the source electrode and the drain electrode are formed after the gate electrode has been formed. That is, ordinarily, formation of the gate electrode and formation of the source electrode and the drain electrode are separately performed. Therefore, in the processes progressed to the stage where the formation of the source electrode and the drain electrode is completed, four patterning steps are performed, and four photomasks are used in the patterning steps. To complete the formation of the pixel electrode, two more patterning steps are performed. That is, in the above case, the number of the patterning steps is six, and the number of the photomasks used in the patterning steps is accordingly six.
At present, improvements in the throughput (quantity that can be processed in a unit time) and the yield (ratio of the number of finished products to the number of inputs to a manufacturing line) are strongly demanded in the field of the manufacture of field-effect transistors such as thin-film transistors and display devices using the field-effect transistors.
However, in the conventional procedure, since the number of steps in the conventional procedure is large, the time required for the manufacture of field-effect transistors and display devices cannot easily be reduced, and it is difficult to improve the yield. For example, because of shrinkage of a substrate or for other causes, a positional offset of a fine pattern formed in a subsequent patterning step can unexpectedly occur. The positional offset of the pattern results in the manufacture of defective products as well as in reduction in the yield. For example, in a step of forming an opening (contact hole) by performing patterning to form the source electrode and the drain electrode, the position of the opening is offset from the source region and the drain region where the opening is intended to be provided.
A case can be in which even when a positional offset of a pattern is caused at one patterning step, the offset is as slight as that falling within an allowable tolerance, and no adverse effects are thereby caused on the operation of a finished display device. However, when a number of patterning steps are repeatedly performed, the slight positional offset is enlarged, thereby increasing the probability of defective-product occurrence.
The present invention has been made in view of the above, and an object of the present invention is therefore to improve the yield by reducing the number of patterning steps and to reduce the manufacturing time by reducing the number of photomasks and by reducing the number of patterning steps in a way that incorporates a plurality of steps into one step.
According to the present invention, a surface of a crystalline semiconductor is oxidized using an oxidizing water solution, such as ozone water solution or hydrogen peroxide water solution, and an oxide film is thereby formed. With the oxide film being used as an etch stop, the gate electrode, the source electrode, and the drain electrode of a field-effect transistor are simultaneously formed from a same starting film. After the gate electrode, the source electrode, and the drain electrode have been formed, the electrodes are heated at a temperature of 800xc2x0 C. or higher for a predetermined time in an ambient of an inert gas. In this case, either an argon gas or a nitrogen gas is used as the inert gas.
Further, according to the present invention, there is provided a manufacturing method for a field-effect transistor, comprising: forming a first insulation film on a crystalline semiconductor; forming a gate insulation film on a portion of the crystalline semiconductor by patterning the first insulation film; forming an oxide film by oxidizing a surface of the crystalline semiconductor by using an oxidizing water solution, such as ozone water solution or hydrogen peroxide water solution; forming a conductive film on the oxide film and the gate insulation film, the conductive film comprising a semiconductor film containing an n-type impurity; simultaneously forming a gate electrode, a source electrode, a drain electrode by patterning the conductive film; and introducing an n-type impurity to the crystalline semiconductor by using the gate electrode, the source electrode, and the drain electrode as masks. In the above stage, the oxide film exists between the source electrode and the crystalline semiconductor, and between the drain electrode and the crystalline semiconductor, the oxide film containing SiOx (0 less than X less than 2) and SiO2. Thereafter, the crystalline semiconductor, the oxide film, the gate insulation film, the gate electrode, the source electrode, and the drain electrode are heated in an inert gas ambient, for example, a nitrogen ambient, at a temperature of from 800xc2x0 C. to 1050xc2x0 C. for a time period of from 30 minutes to 4 hours. By the heating, the n-type impurity contained in each of the source electrode and the drain electrode can be dispersed to the crystalline semiconductor, and in addition, the n-type impurity can be activated. Concurrently, the heating works to reduce the contact resistance between the source electrode and the crystalline semiconductor and the contact resistance between the drain electrode and the crystalline semiconductor. Instead of using the semiconductor film containing the n-type impurity, a semiconductor film containing a p-type impurity may be used; and instead of introducing the n-type impurity to the crystalline semiconductor, the p-type impurity may be introduced thereto.
According to the present invention, the oxide film, which has been formed such that the surface of the crystalline semiconductor is oxidized using one of the oxidizing water solution such as ozone water solution or hydrogen peroxide water solution, operates as an etch stop at the time of simultaneously forming the gate electrode, the source electrode, and the drain electrode from the conductive film. Therefore, the crystalline semiconductor is remained unetched. Ozone and hydrogen peroxide used to form the oxide film are water-soluble and each known as an oxidizer that oxidizes other materials. The conductive film needs to be formed using a material having a melting point higher than the temperature set in the above-described heating. In addition, the conductive film may be formed by overlaying metal having a melting point of 800xc2x0 C. or higher on the crystalline silicon containing the n-type impurity. The metal may be selected from, for example, copper, palladium, chromium, cobalt, titanium, molybdenum, niobium, tantalum, and tungsten. Alternatively, the metal may be selected from metal silicide substrates such as cobalt silicide, titanium silicide, molybdenum silicide, niobium silicide, tantalum silicide, and tungsten silicide. Still alternatively, the conductive film may be formed in combination with a metal nitride substance, such as titanium nitride, tantalum nitride, or tungsten nitride.
In the present invention, the crystalline semiconductor is one of monocrystalline and polycrystalline semiconductors and is not limited to the form of a thin film. When using the crystalline semiconductor in the form of a thin film, a semiconductor film may be formed on the upper side of the substrate, and a crystalline semiconductor film formed by crystallizing the semiconductor film may be used. According to the present invention, since the heat treatment is performed at a temperature of from 800xc2x0 C. to 1050xc2x0 C., a usable substrate is limited to a substrate, such as a quartz substrate, a silicon substrate, or a stainless steel substrate, which is not deformable because of the heat treatment.
The present invention enables the use of such a method as described hereunder. Before forming a conductive film for the use of forming a gate electrode, a source electrode, and a drain electrode, the n-type impurity is introduced to a crystalline semiconductor by using the gate insulation film. Then, the gate electrode, the source electrode, and the drain electrode are formed. Thereafter, the n-type impurity is introduced again to the crystalline semiconductor, and a heat treatment is performed at a temperature of from 800xc2x0 C. to 1050xc2x0 C. In this case, a p-type impurity may be introduced to the semiconductor instead of the n-type impurity. In addition, as a material for forming the conductive film, a semiconductor including the n-type impurity or the p-type impurity need not always be used.
The above-described manufacturing method for a field-effect transistor may be applied to the manufacture of a display device using field-effect transistors manufactured according to the manufacturing method. Examples of the display device include an active matrix liquid crystal display device and an active matrix display device using light emitting devices (LEDs).
According to another aspect of the present invention, a field-effect transistor manufactured by using the manufacturing method for a field-effect transistor includes an island-like crystalline semiconductor film on the upper side of a substrate, a gate insulation film formed in a portion of the island-like crystalline semiconductor film, a source electrode and a drain electrode formed on the island-like crystalline semiconductor film, and a gate electrode formed on the gate insulation film, wherein the island-like crystalline semiconductor film includes a source region, a drain region, a low-density impurity region (LDD region), and a channel region; and SiOx (0 less than X less than 2) between the source electrode and source region and between the drain electrode and the drain region.